1. Field
The present invention relates to an apparatus, a method, and a system for testing an integrated-circuit (IC) chip.
2. Description of the Related Art
One of the most popular methods to test an integrated-circuit (IC) chip includes applying test data to an input of the IC chip and comparing an output of the IC chip with a predetermined expected value or expected result (see, for example, Korean Patent Laid-Open Publication No. 10-2012-0102876). However, in the case of an IC chip including a sequential logic having storage elements such as flip-flops (F/Fs), it is not easy to apply a desired value to a flip-flop in the IC chip or to detect the value of the flip-flop from the outside.
The scan design method is one of the design-for-testability (DFT) methods, which is used to increase controllability and observability of a circuit in the IC chip. The scan design method provides test data having small size and high fault coverage by using an automatic test pattern generator (ATPG) that is software for automatically generating a test pattern based on structural information of the circuit.
In other words, the scan design enables the circuit having a sequential logic in the IC chip to be easily controlled and observed from the outside by taking the sequential logic as a combinational logic while performing a scan test and the size of the test data to be minimized by using the ATPG. The test data obtained via the scan design and the ATPG software include at least one scan pattern. In the scan test, scan patterns can have a predetermined order.
A typical scan test process is described below.
Step 1: Primary input test data are applied to a primary input port of an IC chip.
Step 2: A scan enable signal is applied to a scan enable port, to set the IC chip to a scan mode.
Step 3: A scan pattern is shifted in via a scan input port, to load the scan pattern into flip-flops on a scan path. Hereinafter, a shift-in to the scan input port or a shift-out from a scan output port is simply referred to as a “shift” in some cases. A shift period for shifting the scan pattern is the reciprocal of a shift frequency of a clock applied to a clock input port. The scan pattern loaded into the scan path is applied to the combinational logic. An output result outputted from a primary output port in response to the scan pattern applied to the combinational logic is compared with an expected primary output value. When a result of the comparison indicates a mismatch, the corresponding IC chip is determined to be faulty.
Step 4: A scan disable signal is applied to the scan enable port, to switch the mode of the IC chip from the scan mode to a functional mode. In the functional mode, when a clock signal is applied to the clock input port, the flip-flop captures an output value of the combinational logic. This operation is referred to as a “scan capture”, and the mode in which the scan capture is performed is referred to as a “scan capture mode”.
Step 5: A scan enable signal is applied to the scan enable port, to switch the mode of the IC chip from the functional mode to the scan mode.
Step 6: The value captured in the flip-flop on the scan path is shifted-out and an output pattern is unloaded from the scan output port.
Step 7: The unloaded output pattern is compared with a predetermined expected pattern, to determine whether or not the IC chip is normal. The expected pattern is a value or an output pattern known or expected before the test, which is a scan pattern supposed to be outputted from the scan output port after applying the primary input test data and the scan pattern and performing the scan capture when the IC chip is normal. When a result of the comparison at Step 3 indicates a match and a result of the comparison at Step 7 indicates a match, the test result is a “PASS”, which means that the IC chip is normal. Otherwise, the test result is a “FAIL”, which means that the IC chip is faulty. The test PASS means that the IC is fault free, and the test FAIL means that the IC chip is defective.
The type of scan test is roughly divided into a stuck-at-fault test and a delay-fault test. The stuck-at-fault means a state in which a signal line on the IC is unintendedly fixed to a value of logical 0 or 1. The delay fault means a state in which the spec of the IC chip cannot be satisfied due to a delay time when transferring a signal value through a signal line or a signal path on the IC chip.
The delay-fault test includes a transition delay test and a path delay test, and is also referred to as an “at-speed test”. The transition delay test is to find a delay time problem in the transition of the signal value from 0 to 1 or from 1 to 0 at a node or on a signal line on the IC chip. The path delay test is to find a delay time problem in the transition of the signal value from 0 to 1 or from 1 to 0 on a signal path on the IC chip.
A general delay-fault test method includes a launch-on-capture method and a launch-on-shift method, which also includes a loading step of shifting in a scan pattern for the delay-fault test to a scan path and an unloading step of shifting out a delay-fault test result captured in a flip-flop on the scan path.
Such a scan test necessitates as many clock pulses for the shifting operation as the number of flip-flops on the scan path. This causes a considerable time to be taken to perform the shift-in and shift-out operations. However, a frequency of the clock signal for shifting the scan pattern to the scan path, i.e., a shift frequency, cannot be simply increased to reduce the test time.
For example, a simple increase of the shift frequency may cause an over kill problem in which a normal chip is determined to be defective due to a problem of power consumption or critical path delay time.
Further, as the power consumption of the IC chip is getting lowered due to a design for low-power consumption as well as a deep sub-micron (DSM) manufacturing process or a low-power manufacturing process, an influence of a power supply noise on the operating frequency of the IC chip has increased. As the IC chip generates more switching activities in the scan mode than in the functional mode, an additional delay on a signal line caused by the power supply noise due to the switching activities may incur an over kill during a delay test (i.e., a delay test over kill). Therefore, there is a technical limit in simply increasing the shift frequency.
Moreover, the signal integrity problem related to a signal crosstalk between signal lines on the IC chip has become more critical than ever as the DSM process becomes dominant. The signal crosstalk between the signal lines may become severe due to the considerable switching activities in the scan mode. Therefore, an additional delay on the signal line caused by the signal crosstalk between the signal lines during the delay test may incur a delay test over kill.
Further, when the shift frequency is searched based on the power consumption of the scan pattern, even if the power consumption does not exceed the spec of the IC chip, a scan test error may be incurred due to an IR-drop or ground-bounce caused by excessive circuit switching activities by the scan test characteristics and process variation.
For example, when performing a delay test using a scan pattern, an IR-drop, i.e., a voltage drop, may cause an additional delay on a specific signal line, which may lead to a delay test over kill. On the contrary, even when the power consumption of the scan pattern exceeds the spec of the IC chip, the IR-drop or ground-bounce problem may not occur due to manufacturing process and design characteristic of the IC. Therefore, there is a technical limit in searching the optimum shift frequency for the IC chip simply based on the power consumption. Further, when searching the maximum shift frequency only based on the power consumption of the scan pattern, even if the power consumption does not exceed the spec of the IC, an increased shift frequency may cause a critical path timing problem on the scan path.
When the shift frequency is increased, there may be a case where a critical path timing problem occurs on the scan path but no logical problem occurs due to the scan pattern. That is, a case of a false critical path may be occurred in a specific scan shift cycle according to bit values on the critical path of the scan path.
For example, when a shift operation is performed with a high shift frequency after storing two consecutive logical-0 bits in two flip-flops constituting a critical path on the scan path, a critical path delay time problem may occur, in which a signal for the logical-0 bit stored in a flip-flop located at the beginning of the critical path may not arrive at the next flip-flop in a normal shift time. However, in this case, there occurs no logical problem in the bits stored in the two flip-flops constituting the critical path by the shift operation, which is defined as the false critical path.
In addition, in the case of a low-power IC chip employing the technique of multiple voltage islands or multiple voltage domains or regions, every voltage region has different allowable power consumptions, because a high voltage is supplied to a design region requiring high speed performance and a relatively low voltage is supplied to other design regions.